1. Field of the Invention
The present invention relates to a preprocessor which is used to automate operation of changing a hardware description in accordance with a configuration. The present invention also relates to an integrated circuit design system using the preprocessor and an integrated circuit design method by the system. The present invention is particularly suitable for a system which automatically creates IP and software IP in accordance with user's designation, which creates a circuit description file which can designate synchronous/asynchronous reset of a flip-flop or change the cluster combination of a gated clock.
2. Description of the Related Art
Conventionally, an integrated circuit design system is designed to have an arrangement as shown in FIG. 1. A computer system used to design such an integrated circuit and a method thereof are described in, e.g., U.S. Pat. No. 5,987,239 issued to Graham Kirsch, “COMPUTER SYSTEM AND METHOD FOR BUILDING A HARDWARE DESCRIPTION LANGUAGE REPRESENTATION OF CONTROL LOGIC FOR A COMPLEX DIGITAL SYSTEM”, Nov. 16, 1999.
A circuit description file 11 which is described by a user using an existing language (Verilog-HDL: Verilog-Hardware Description Language or VHDL: Very high speed integrated circuits Hardware Description Language) and a logic synthesis control script file 12 (script file which controls a logic synthesis program) are logically synthesized by a logic synthesis program 14 of a processor (logic synthesis tool or computer) 13. The logic synthesis program 14 executes processing for converting the circuit description file 11 into a circuit description file using a “cell” serving as a basic unit of a circuit to create a netlist 15. The netlist 15 is processed by a layout wiring program (a program which lays out cells and wirings) 16 to determine the layout of the cells and wirings so that the circuit of a chip (semiconductor integrated circuit) 17 is designed.
In the above conventional integrated circuit design system, to describe a synchronous reset circuit or asynchronous reset circuit using an existing language such as Verilog-HDL or VHDL, two descriptions for synchronous reset and asynchronous reset must be manually generated. In addition, when a flip-flop should be changed to a gated clock to reduce power consumption, the optimum cluster design method changes because conditions such as the optimum number of flip-flops to be put into one cluster and flip-flops that are laid out close to each other in a chip and should therefore be cluster-combined change depending on various factors. Examples of factors are:
(1) The difference in physical technology of a semiconductor integrated circuit (IC or LSI).
(2) The difference in circuit operation pattern, i.e., the manner a user application uses the circuit.
(3) The layout of circuits in a chip.
However, convergence to the optimum value is conventionally difficult because descriptions for synchronous reset and asynchronous reset are manually generated, or a circuit for forming a gated clock is inserted by trial and error. In addition, to insert a circuit to form a gated clock, peripheral circuits must be corrected. If the circuit scale is large, the number of correction portions may be as large as several hundreds, although the correction concerns only the periphery of the description of the flip-flop. Furthermore, bugs are unavoidable in manual correction. Hence, function verification operation is necessary every time a circuit is corrected. The circuit scale and complexity of LSIs are rapidly increasing. Accordingly, the time required for verification operation also becomes long. This partly prolongs the LSI development period or increases the cost.
A tool which automatically inserts a circuit for gated clock formation already exists (e.g., Marcus Blüml et al., “A Workbench for Generation of Component Models”, 0-8186-4350-1/93 1993 IEEE, pp. 466–471). However, this tool cannot meet a particular requirement to, e.g., combine designated clusters and is not necessarily satisfactory.